CS2501 Overview
The CS2501 is a system-clocking device incorporating a programmable phase-locked loop (PLL). The hybrid analog/ digital PLL architecture comprises a delta-sigma fractional-N analog PLL and a digital frequency-locked loop (FLL). The CS2501 enables clock generation from a stable timing reference clock. The device can generate low-jitter clocks from a noisy clock reference at frequencies as low as 50 Hz. An internal oscillator can provide the timing reference clock, enabling a reduction in external component requirements.
The CS2501 can be configured using a control interface supporting I2C and SPI modes of operation. The CS2501 can be powered from a single 1.8 V or 3.3 V supply. The device combines high performance with low power consumption.
The CS2501 is available in commercial-grade 10-pin TSSOP package for operation from –40°C to +85°C. The device is also available in the AEC-Q100-qualified grade-2 package for operation from –40°C to +105°C.
Product Features
High-performance analog/digital phase locked loop
Fractional clock multiplier and jitter reduction using hybrid analog/digital PLL
Generates low-jitter 6 to 75 MHz clock (CLK_OUT), synchronized to a 50 Hz to 30 MHz low-quality or intermittent frequency reference (CLK_IN)
Flexible timing reference source
External clock, external crystal or built-in oscillator
Great performance
High resolution PLL ratio (1 PPM)
18 psRMS period jitter
18 psRMS period jitter with internal reference
Glitchless clock output generated from intermittent input
I2C/SPI control port
Configurable auxiliary clock/status output
Minimal board space required
No external analog loop-filter components
Pin-to-pin, register map, and control compatible with CS2100 and CS2300
Single-supply operation at 1.8 V or 3.3 V
Parametric Specifications
| Host Interface | Yes |
| Clock Multiplier / Jitter Removal | Yes |
| Frequency Synth / Clock Generator | No |
| Output Frequency Range (MHz) | 6-75 |
| Reference Frequency Range (MHz) | 8-75 |
| Power Supply (V) | 1.8-3.3 |
| One-Time Programmable | No |
| Target Market | Automotive; Pro Audio |
| Package | 10 TSSOP |
Design Resources
CS2501-CZR
CS2501-DZ
CS2501-DZR
CS2501 Datasheet
CDB-CLOCKING User Guide
CDB-CLOCKING-MB Schematic and Block Diagram
CDB2501-DC-SD Schematic and Layout
CS2501 Migration Document
CS2XXX Device ID Compatibility
CS2501 Datasheet (Chinese)
CS2501 Datasheet (Japanese)
Evaluation Boards
CS2501 Clocking Evaluation Board (CDB2501-DC-SD)
The CDB2501-DC-SD evaluates the Cirrus Logic CS2501 high-performance clocking device. A daughter card for the CDBCLOCKING-MB motherboard, it supports a range of clock inputs and outputs and full device configuration.
CS2500, CS2501 and CS2600 Clocking Evaluation Board (CDBCLOCKING-MB)
The CDBCLOCKING-MB is the motherboard for evaluating the Cirrus Logic CS2500, CS2501 and CS2600 high-performance clocking devices. It supports a range of clock inputs and outputs and accepts the device-specific daughter cards below.
Software Packages
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Timing Series
- Timing
CS2500
ActiveFractional-N Clock Synthesizer and Multiplier
View Datasheet - Timing
CS2501
ActiveFractional-N Clock Multiplier
View Datasheet - Timing
CS2600
ActiveFractional-N Clock Synthesizer and Multiplier
View Datasheet
Pricing
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