WM8233 Overview
The WM8233 is a 16-bit analog front end/digitizer IC which processes and digitizes the analog output signals from CCD sensors or Contact Image Sensors (CIS) at pixel sample rates of up to 22.5MSPS. The device has six analog signal processing channels each of which contains reset level clamping, correlated double sampling (also sample and hold), programmable gain, Automatic Gain Control (AGC) and offset adjust functions. The output from each of these channels is time multiplexed, in pairs, into three high-speed 16-bit analog to Digital Converters. The digital data is available in a variety of output formats via the flexible data port. The WM8233 has a user selectable LVDS or CMOS output architecture. An internal 8-bit DAC is supplied for internal reference level generation. This may be used during CDS to reference CIS signals or during Clamping to clamp CCD signals. An external reference level may also be supplied. ADC references are generated internally, ensuring optimum performance from the device. A programmable automatic Black-Level Calibration function is available to adjust the DC offset of the output data. The WM8233 features a sensor timing clock generator for both CCD and CIS sensors. The clock generator can accept a slow or fast reference clock input and also has a flexible timing adjustment function for output timing clocks to allow use of many different sensors.
Product Features
70MSPS conversion rate
16 bit ADC resolution
Current consumption – 350mA
3.3V single supply operation
Sample and hold /correlated double sampling
Programmable offset adjust (8-bit resolution)
Flexible clamp timing
Pixel clamp / line clamp mode
Programmable clamp voltage
Programmable CIS/CCD timing generator
Internally generated voltage references
Compliant for spread spectrum clock
LVDS/CMOS output options
Complete on chip clock generator. MCLK 5 MHz to 35 MHz
Internal timing adjustment
Automatic gain control
Automatic Black Level Calibration
56-lead QFN package 8mm x 8mm
Serial control interface
Parametric Specifications
| Package | 56 QFN |
| Output Format | LVDS 10/16 bit 5 pair|LVDS 10/16 bit 3 pair|LVDS 12 bit 4 pair|CMOS 10 bit |
| Control Interface | Serial |
| Speed (MSPS) | 210 |
| Resolution (bits) | 16 |
| Input PGA (bits) | 12 |
| Offset (bits) | 8 |
| Power Supply (V) | 2.97-3.63 |
| Power Consumption (mW) | 1287 |
Design Resources
Schematic and Layout
6109-EV1-REV1 Schematic Layout
REV 1 | 1 MbSeptember 2008
Application Note
AC Coupling Capacitor Selection for Wolfson AFE Devices
WAN_0127 | 72 KbFebruary 2004
Application Note
QFN Package PCB Footprint and Soldering Guidelines
WAN_0118 | 740 KbSeptember 2014